[sdiy] DIY Parallel DAC

[Veronica Merryfield]

On 2011-07-30, at 10:39 PM, Eric Brombaugh wrote:

> * What's your principle objection to serial DACs? Speed? Circuit complexity? There are a lot of them out there, some capable of sample rates in excess of 10 MHz that would be perfectly fine for synthesis applications. If you're already committed to using an FPGA and you've got SPI or I2C interfaces for the parameter inputs it's not much of a stretch to use something similar for the audio output too. And while you're at it don't discount the possibility of using Sigma/Delta DACs for audio - they're easy to use, inexpensive and provide excellent audio specs.

I was thinking something like this too. Since Matthew is going to use a FPGA, it should be easy enough to use a serial DAC (Sigma/Delta - AK4382 for instance). The FPGA can handle the timing and serial output which would be a much simpler proposition than creating a resistor ladder DAC. 

The possible issue may be a variable clock in the waveform generation I guess which would make using a serial or SD DAC a bit difficult, but not impossible. If this is the case, the DAC is clocked at a constant oversampled rate. The sample value is output at the rate but just that value update rate internally is different. As long as the logic simply places the value to be output in a location the output code can read, the timing could be decoupled but it will need some logic to avoid conflicts, or at least working from a common higher rate clock. Tricky, but far from impossible.

To the resistor precision question, it boils down to the network error being less than one bit, or rather, less than half a bit. There is a lot more to it, but that would get you pretty close. So a 0.1% resistor network would probably be good to 9-bit (1 in 512) with a simplistic analysis. But, and it is a big one, there are a lot of issues that need to be considered... is the variation in the logic level output at or less than 0.1%? Do you need a different reference scheme, and if so, is the switch differences at or less than 0.1%, how do cumulative 0.1% errors combine (worst and best case), what does the non0linearity look like for that, and so on.