[sdiy] DIY Parallel DAC
Paul Perry
pfperry at melbpc.org.au
Sun Jul 31 08:40:54 CEST 2011
I wonder just how much variation is there likely to be on the output levels
from various elements of the FGPA? Inaccuracies there might relieve you of
worry about (pointless) precision elsewhere.
paul perry Melbourne Australia
----- Original Message ----- >> Due to the lack of sensibly-priced parallel
load DACs (and the fact I don't want to muck around with serial timing for
waveform generation) I am looking to drive a R-2R ladder DAC directly from
an FPGA.
>>
>> Other than buffering the output and using half-decent resistors (looking
>> at some Vishay 0.1% at $1.52 a piece, in easy-to-solder 0805 packages) is
>> there anything I should be aware of? (And can I get away with lower
>> precision/cheaper resistors?)
>>
>> Working on a 3.3V reference, 1k and 2k resistors.
>>
>> For those who are curious:
>>
>> This is actually a Next Generation of the wavetable design I'm playing
>> with at the moment. Whilst I'm trying to use "legacy" parts in the first
>> design (venerable 8-bit DAC, EPROMs,) the complexity of the decoding
>> logic required drove me to use a CPLD to generate ROM addresses from the
>> incoming clock signal.
>>
>> The FPGA design crams all of what I have conceived so far into a single
>> part - MIDI note, wave select, sub-octave select (I'm using 3 ROMs+DACs
>> per voice, octave and wave individually selectable) - input is an I2C or
>> SPI message, output is the logic driving the resistor ladder.
>>
>> Cheers
>>
>> M
>> --
>> Matthew Smith
>>
>> Business: http://www.smiffytech.com
>> Blog: http://www.smiffysplace.com
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>> Twitter: http://twitter.com/smiffy
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