[sdiy] DIY Parallel DAC

[Eric Brombaugh]

A few points:

* How many bits you looking for? The more bits you want the more critical the accuracy of your resistors is, and the more sensitive the system becomes to things like impedance variations in the buffers driving the ladder and noise on the VDD that's running the buffers.

* What parallel DACs have you looked at? There are some 10/12/14-bit parallel DACs for RF signal generation that are reasonably priced (especially compared to $1.52/ea for all the 0.1% resistors you're going to need) and should work fine at audio rates as well.

* What's your principle objection to serial DACs? Speed? Circuit complexity? There are a lot of them out there, some capable of sample rates in excess of 10 MHz that would be perfectly fine for synthesis applications. If you're already committed to using an FPGA and you've got SPI or I2C interfaces for the parameter inputs it's not much of a stretch to use something similar for the audio output too. And while you're at it don't discount the possibility of using Sigma/Delta DACs for audio - they're easy to use, inexpensive and provide excellent audio specs.

Eric

On Jul 30, 2011, at 10:23 PM, Matthew Smith wrote:

> Hi Folks
> 
> Due to the lack of sensibly-priced parallel load DACs (and the fact I don't want to muck around with serial timing for waveform generation) I am looking to drive a R-2R ladder DAC directly from an FPGA.
> 
> Other than buffering the output and using half-decent resistors (looking at some Vishay 0.1% at $1.52 a piece, in easy-to-solder 0805 packages) is there anything I should be aware of? (And can I get away with lower precision/cheaper resistors?)
> 
> Working on a 3.3V reference, 1k and 2k resistors.
> 
> For those who are curious:
> 
> This is actually a Next Generation of the wavetable design I'm playing with at the moment. Whilst I'm trying to use "legacy" parts in the first design (venerable 8-bit DAC, EPROMs,) the complexity of the decoding logic required drove me to use a CPLD to generate ROM addresses from the incoming clock signal.
> 
> The FPGA design crams all of what I have conceived so far into a single part - MIDI note, wave select, sub-octave select (I'm using 3 ROMs+DACs per voice, octave and wave individually selectable) - input is an I2C or SPI message, output is the logic driving the resistor ladder.
> 
> Cheers
> 
> M
> -- 
> Matthew Smith
> 
> Business: http://www.smiffytech.com
> Blog:     http://www.smiffysplace.com
> Linkedin: http://www.linkedin.com/in/smiffy
> Flickr:   http://www.flickr.com/photos/msmiffy
> Twitter:  http://twitter.com/smiffy
> _______________________________________________
> Synth-diy mailing list
> Synth-diy at dropmix.xs4all.nl
> http://dropmix.xs4all.nl/mailman/listinfo/synth-diy