[sdiy] FPGAs

[Scott Gravenhorst]

Thomas Strathmann <thomas at pdp7.org> wrote:
>On 1/27/11 06:11 , Dave Manley wrote:
>>> Am I right in thinking that I'd need to learn VHDL, or am I barking up
>>> the wrong logic array?
>>
>> No one needs to learn VHDL.
>>
>> Learn Verilog instead.
>
>I like Verilog better myself (because I'm from the C side of town so to 
>speak), but VHDL is not bad either (if I were to use it I might learn to 
>like it). One should probably try to read a few examples of the same 
>functionality implemented in Verilog and VHDL and compare them side by 
>side. Also take into consideration what your tools support, for which 
>language you get more and better books (from your local library), 
>whether you get more free source code for one or the other and so on.

I did pretty much what you said, look at a few examples of both languages describing
the same design.  I liked Verilog better because of it's C-like structure.  My
approach might be unusual, but I learned Verilog by using web-based tutorials so I
have no book nor a recommendation for one.  Here is the Verilog tutorial I liked the
best: http://www.asic-world.com/verilog/veritut.html

Also if you poke around in my FPGA web pages (see sig) you can find Verilog code for
most of my synthesizer designs.  These designs work, but I don't hold myself out as a
designer of "best practice" code - though I think it's gotten better as I've gone
forward.  I do try to comment fairly profusely.

>BTW, does the rule of thumb that VHDL dominates in Europe whereas 
>Verilog is predominant in America (and maybe other parts of the world) 
>still hold?
>
>	Thomas

I've developed a number of friendships with other FPGA people, and I'd say that in my
experience, yes, it still holds true.

-- ScottG
________________________________________________________________________
-- Scott Gravenhorst
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