[sdiy] Wavetables

[Dave Manley]

On 1/24/2011 11:21 AM, Scott Gravenhorst wrote:
> Paul Maddox<paul.Maddox.mail-list at Synth.net>  wrote:
>> Gotta agree with Scott though, FPGAs are made for this kind of
>> thing... though I *WISH* they had more onboard RAM/EEPROM :-)
>
> Amen to that - and STATIC RAM.
>
> Larger FPGAs have more internal RAM, but I'd prefer megawords (16bit) of static RAM...  But
> for some reason, static RAMs are expensive.


Typical SRAM requires 6 transistors per bit - so a megaword of SRAM takes
100,663,296 transistors just for the storage, and then you still have to
break that into reasonable sized blocks, add in address decoders,
read multiplexing, buffering to distribute control and data to 100M
transistors, etc.

If you consider also there will be defects that make part of the memory
unusable, then you need to add in redundant cells, a way to select them,
and potentially error detection and correction.

Even at 45nm, 100M of anything starts to add up (in this case just
this memory would be roughly 280 mils on a side*).

-Dave

*Based on cell size info from Wikipeda.  I can run a ram compiler
tomorrow and verify, but the number doesn't seems ridiculously
unreasonable. SRAM is expensive which is why DRAM exists.

P.S. There is 1T-SRAM, which is smaller.  Not sure what Xilinx uses,
but I'd guess 6T.