[sdiy] Simulating SSM2164 circuits with LTspice

Olivier Gillet ol.gillet at gmail.com
Sat Jan 29 11:41:52 CET 2011


Hi all,

I know this has been discussed in the past, but I couldn't find any
definitive word on this in the archives...

I am trying to simulate SSM2164-based circuits in LTSpice. I'm very,
very new to this so here's what I did for the SSM2164 behavioral
model:

* SSM2164 VCA cell
.SUBCKT SSM2164 IN OUT CV
* The two transistors in the input's differential pair have the same base
* current, hence the same Vbe. The second transistor is referenced to
* ground so IN is virtually grounded.
R1 IN 0 1e-5
* Models 5k impedance for the CV input
R2 CV 0 5k
* Stability network
R3 IN 1 560
C1 1 0 560p
* Current gain expression
G1 OUT 0 VALUE={-I(R1)*PWR(10, -V(CV) * 1.5)}
.ENDS


The R1 thing is particularly horrid, but I didn't find any other way
of specifying that IN is at ground potential.

I can simulate Mike Irwin's linear VCA with this, yeah! However, I
cannot simulate a one-pole LP cell - resolution doesn't converge. At
this stage I don't know if this is something wrong with the LP circuit
(looks good on breadboard and in theory), my model, or something I
have not set up properly in Spice.

Here are my files:
http://dl.dropbox.com/u/612135/simulations.zip

How could my model be fixed to allow the simulation of the LP cell to work?

And if you have some simulations tips and/or links to good tutorials
let me know!

Thanks!
Olivier


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