[sdiy] Digital ADSR - perceivable staircase?

[ASSI]

On Tuesday 15 February 2011, David G. Dixon wrote:
> Talk about hammering a nail with a pile driver!

Says the man who uses a Rube Goldberg contraption for what could be more 
succinctly done with a multiplying DAC?  :-)

There is no right or wrong solution to this problem and everybody gets there 
from a different background and settles in a different spot.  To take some 
sting out of my remark, your solution probably is the right one if you want 
to modulate the same signal with both a CV and a digitally generated signal.  
It certainly isn't if you need more than about 10 bit of precision (and to 
get there with the 2164 will require some heavy lifting).

As for Scott's digital EG: it is essential that the computation is done in 
high precision if you want to have a large range of timing values or 
envelope rates.  About 1 bit per 4 dB timing resolution is a good initial 
guess, so the 28 bit Scott uses should be good for around a 400,000:1 range.  
That is certainly nothing too exalted to ask from an EG.  How many bits you 
use at the target of that modulation is an entirely different question.  
Same thing as with phase accumulators, really: you need more internal 
precision than you will use externally.


Achim.
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