[sdiy] Digital ADSR - perceivable staircase?

[David G. Dixon]

> Should have stated the purpose: VCA envelope, VCF envelope. No
> oscillators will be harmed by this subsystem. (Keeping my design simple,
> there are no VCOs in there. Initial wave comes from the wavetable DCO
> (256 samples per cycle,) LFO will only provide modulation to VCA, VCF
> and will likewise be a DCO, but with a much longer wavetable (1024 or
> even 2048 samples per cycle.)

I'm taking a different approach to all these problems myself.  My ultimate
plan (what I'm working towards, anyway) is to VC everything with 2164 VCAs
(I'm nearly there now), keeping all the signal and CV streams mostly analog,
and then simply control the 2164s with DACs rather than panel pots.  To me,
this seems much easier, although I realize this isn't necessarily what you
are after.  It just seems like you're giving yourself a very hard row to
hoe, trying to force a (digital) square peg into a (analog) round hole.
Think about it: 16-bit accuracy for a lousy envelope!  Talk about hammering
a nail with a pile driver!