[sdiy] Wavetable Design Update

[ASSI]

On Sunday 06 February 2011, Matthew Smith wrote:
> As my Verilog/VHDL books are (hopefully) somewhere between here and the
> USA, I've started off using schematic capture.  My counters are 74XX163s
> - haven't quite been able to figure out how to use a pair of them and
> reset to zero when I reach 128.

You don't need to reset anything at all if you only want to use 7 bits 
instead of eight.  You just don't care what that last bit is doing and the 
rest of the counter is OK as is.  Otherwise, you could surely build that 
counter from D-FF or T-FF even in schematic capture?



Achim.
-- 
+<[Q+ Matrix-12 WAVE#46+305 Neuron microQkb Andromeda XTk Blofeld]>+

SD adaptation for Waldorf microQ V2.22R2:
http://Synth.Stromeko.net/Downloads.html#WaldorfSDada