[sdiy] Wavetable Design Update

Matthew Smith matt at smiffytech.com
Sun Feb 6 09:59:55 CET 2011


Quoth Dave Manley at 06/02/11 19:19...
...
> You would only reduce the table depth at higher midi notes, and use
> the full 256 entries at low frequencies.  The counter change is simple -
> instead of adding 1 to the counter you add 2 for 128 deep, or 4 for
> 64 deep.

Sounds like a job for Verilog, once I get there (or, more to the point, 
when the books get HERE.) Currently doing my CPLD design with simulated 
74XX devices through schematic capture.

But so long as my hardware design supports all alternatives, I can 
re-FLASH to my heart's content.  But nice to know I don't need 2 
versions of the EEPROM - the only non-ISP-able part of the system :-)

Cheers

M

-- 
Matthew Smith
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