[sdiy] Wavetable Design Update

[Dave Manley]

On 2/6/2011 12:13 AM, Matthew Smith wrote:
> Quoth ASSI at 06/02/11 18:10...
>> A synchronous counter of power of 2 length does that all by itself with no extra logic.
>
> As my Verilog/VHDL books are (hopefully) somewhere between here and the USA, I've started off using schematic capture. My counters are 74XX163s - haven't quite been able to figure out how to use a
> pair of them and reset to zero when I reach 128. I *think* that I just need to couple the resets on both and feed them from QD on the second device, but not sure if this will reset a clock cycle
> early/late - and I have no hardware on which to test it!
>
With 163 type counters (been a very long time) the easy way is
let it count to the max value and then parallel load a value
other than 0.  For your example load 128, and there's no need
to muck with the resets.

This way you don't need a separate decoder to detect the terminal
count.

-Dave