[sdiy] Wavetable Design Update

[Matthew Smith]

Quoth ASSI at 06/02/11 18:10...
> A synchronous counter of power of 2 length does that all by itself with no 
> extra logic.

As my Verilog/VHDL books are (hopefully) somewhere between here and the 
USA, I've started off using schematic capture.  My counters are 74XX163s 
- haven't quite been able to figure out how to use a pair of them and 
reset to zero when I reach 128. I *think* that I just need to couple the 
resets on both and feed them from QD on the second device, but not sure 
if this will reset a clock cycle early/late - and I have no hardware on 
which to test it!

> module counter
...
> Fits into the smallest CPLD with room to spare.

Many thanks for the code - as I'm starting off (or will when the books 
turn up) I need all the practical examples I can get!

>> Not sure what 128-bit would sound like at 'serious' bass frequencies,
> 
> Ask someone with a PPG?

If it can be got away with commercially, It can't be that bad ;-)

Cheers

M


-- 
Matthew Smith

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