[sdiy] Wavetable Design Update

[ASSI]

On Sunday 06 February 2011, Matthew Smith wrote:
> I only went to 256 bit because it made the CPLD design easier! (Didn't
> need to figure out the logic to reset a counter before it overflows and
> goes back to zero.)

A synchronous counter of power of 2 length does that all by itself with no 
extra logic.

module counter
  #(
    parameter NT =  7  // samples per full wave cycle: 2**NT
    )
   (
    clk, ce, rst,
    widx
    );
   input            clk;
   input            ce;
   input            rst;
   output [NT-1:0]  widx;

   reg [NT-1:0]     count;

   always@(posedge clk)
     if(rst)
       count <= 0;
     else
     begin
        if(ce)
          count <= count + 1;
     end

   assign widx = count[NT-1:0];

endmodule

module CPLD
  #(
    parameter NT =  8, // samples per full wave cycle: 2**NT
    parameter NC =  3  // number of counters
    )
   (
    clk, ce, rst,
    widx
    );
   input  [NC-1:0]    clk;
   input              ce;
   input              rst;
   output [NC*NT-1:0] widx;

   counter #(.NT(NT))
   count_i[NC-1:0] (.clk(clk), .ce(ce), .rst(rst), .widx(widx));

endmodule

Fits into the smallest CPLD with room to spare.

> Not sure what 128-bit would sound like at 'serious' bass frequencies,

Ask someone with a PPG?



Achim.
-- 
+<[Q+ Matrix-12 WAVE#46+305 Neuron microQkb Andromeda XTk Blofeld]>+

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