[sdiy] Wavetable Design Update

[Matthew Smith]

Quoth ASSI at 04/02/11 04:30...
...
> Umm... you haven't used up all the registers in the CPLD yet or have you?  
> Just look up the twelve numbers for the highest frequency, have a divider 
> chain in the CPLD and direct it to use the correct output for the octave.  
> Or better yet, add the counter and the 20MHz clock to the CPLD too and have 
> the uC just tell it how often to count for clocking the divider chain once 
> and which output tap to use.  Then, use daisy-chained SPI or a parallel 
> address/data bus compatible with your uC as an interface and have one single 
> uC control an almost unlimited number of CPLD generators.

If I only use the CPLD to drive 1 EEPROM/DAC rather than 2 or 3, I 
should have plenty of capacity to spare.

I won't use this approach in this instance seeing as I hadn't heard of 
CPLDs until the FPGA thread started and I'm only just starting to play 
with the Xilinx ISE software. (Which runs just fine on 64 bit Debian, in 
case I didn't confirm before.)   So, I'll carry on as I am, with the 
phase accumulator approach, but look to do this as a future project - 
and once I've learned Verilog. (Schematic capture may be a painless way 
to start, but it's SLOW!)

> No, I'm not cooking that up.  Aside from the variable frequency aspect that 
> is exactly what a PPG does, only with loads of discrete logic.

And it's the "look at all the discrete logic I can condense into one 
device" that has got me so excited about CPLDs. That and the ISP 
capability and a single 5V supply on the devices I'm looking at.

Cheers

M

-- 
Matthew Smith

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