[sdiy] Wavetable Design Update

[ASSI]

On Wednesday 02 February 2011, Matthew Smith wrote:
> My problem is that given a frequency f, I have to work out timer
> configuration values which are:
> 
> * The number to count up to
> * The prescaler value, if required.
> 
> ...for a given CPU clock frequency.  The frequency range I need to be
> able to calculate is pretty massive - from 2093.00 Hz for MIDI note 0 up
> to  3,211,226.61 Hz for MIDI note 127. Note a) this is to clock 256
> samples per cycle, b) I'm working to 2 decimal places, so really working
> in cHz.

Umm... you haven't used up all the registers in the CPLD yet or have you?  
Just look up the twelve numbers for the highest frequency, have a divider 
chain in the CPLD and direct it to use the correct output for the octave.  
Or better yet, add the counter and the 20MHz clock to the CPLD too and have 
the uC just tell it how often to count for clocking the divider chain once 
and which output tap to use.  Then, use daisy-chained SPI or a parallel 
address/data bus compatible with your uC as an interface and have one single 
uC control an almost unlimited number of CPLD generators.

No, I'm not cooking that up.  Aside from the variable frequency aspect that 
is exactly what a PPG does, only with loads of discrete logic.


Achim.
-- 
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