[sdiy] Prophet VS a phase accumulator design?

[Rainer Buchty]

On Wed, 2 Feb 2011, karl dalen wrote:

> So the low clock speed and long samples are the reason for the ESQ1 
> jittery results? Would the DOC chip have sounded better if they had 
> used the 256 mode x 24osc only?

I doubt it. The jittering is IMO due to the fact that processing all $n 
active oscillators two mandatory DRAM refresh cycles follow. Getting rid 
of that, however, is not possible (unless there's some funky test bit I 
haven't found yet). Even if you switch off all oscillators, you still 
see the DRAM refresh cycles.

Going for 256-byte waves only, however, would eventually have increased 
the processing speed as each voice takes 8 cycles to compute; the 
1MHz/(#osc+2) formula is already simplified as it's really 
8MHz/8*(#osc+2).

OTOH, if the internal wave address lines are open collector, then no 
multi-cycle barrel-shifter or fast multiplier (which is how I mimic it 
single-cycle within my slowly growing FPGA adaptation) is required for 
accumulator and waveram page bit selection.

Rainer