[sdiy] VCO unstable in Spice, stable in real world

[David G. Dixon]

> You don't say what your circuit is exactly, but in the real world it is
> usually necessary to put in some hysteresis around the comparator so that
> it will stay high long enough to discharge the cap.  For example C4 in
> this
> version:
> http://home.comcast.net/~ijfritz/sy_cir2.htm
> If your circuit is oscillating OK (check the zero) then you might have
> some
> stray capacitance in the circuit, or something else providing a lag.  We
> would have to see the actual circuit to get a better idea.

I second that motion.  I had a helluva time simulating a sawcore VCO a year
ago or so, and found that the behaviour of the reset cap (not the integrator
cap, but the small cap in the + feedback loop of the comparator to which Ian
refers) was not well simulated at all.  I also found that when I
breadboarded the circuit, I didn't need this cap, and the circuit performed
admirably (probably due to stray capacitance), but that when I transferred
the circuit to PCB, I did need the cap, but not the same value that the
SPICE model suggested.

In my experience, the correct values of little caps (for stability, speedup,
etc) must often be determined by trial and error, preferably with the aid of
a decent oscilloscope.