[sdiy] A/D weirdness

René Schmitz uzs159 at uni-bonn.de
Wed Dec 28 00:30:05 CET 2011


Hi Karl et al.,

Am 27.12.2011 17:56, schrieb Karl Ekdahl:
> Okay so i reworked the whole thing to use the polling method where
> DOUT is tied to VCC and i check for the first '0' to come in before
> getting the data. I also get both the MSB first and the MSB last data
> and compare them afterwards - no inconsistencies so far which i
> assume means my retrieval algorithm works.
>
>
> However, on that note i'm having a hard time getting my head around
> how to assure i'm polling the data on the right clock edge. I guess
> that i'd have to look real close at propagation delays etc. to figure
> this one out but i figured i'll ask anyway. Can i assume "positive
> clock edge" means "while CLK is positive"? Basically would a code
> like this work? (ugly pseudo code coming up)
>
> do CLK = 0;    CLK = 1; getData while


To sample on the positive clock edge just means that the A/D is shifting
out its data on the _negative_ clock edge. So you sample "half-way"
through the clock cycle, which is where the positive clock edge (i.e. 0
to 1 transition) occurs. You're then furthest away from any
transitioning where the data on Dout can be assumed to be stable (and
you have the least worries about propagation delays, reflections etc).
Actually wether you sample immediately before the pos clock edge or
immediately after it doesn't matter.

I'd maybe try sampling more than once and compare results, if you are
bit-banging, and not using special shift hardware (SPI). So you'd know
at least if your problem is noise in the communication, or wether the
data from the A/D itself is noisy.

So your pseudo code is ok, if you place the timing delays such that:

do
      CLK = 0;
      DELAY
      CLK = 1;
      getData
      DELAY
while


> Programmatically this code retrieves the data *while* CLK is
> positive, but i guess propagation delays may or may not trigger this
> on the clock edge? Just getting myself confused here...

Doesn't matter because there is no change in DOUT on the positive clock
edge.


-- 
uzs159 at uni-bonn.de
http://www.uni-bonn.de/~uzs159



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