[sdiy] A/D weirdness

[ASSI]

Am 22.12.2011 20:25, schrieb Karl Ekdahl:
> So right now both the input and reference is buffered with an opamp
> follower (TLC2254), the +3.3V has a 100uF cap to GND on it.

You really want a low-ESR ceramic cap (100nF) in parallel to that or 
maybe even two (10nF||100nF), depending on where the supply comes from. 
  These caps need to be as close as possible to the IC, SMD preferred. 
Both the supply and the ground return for the buffers and the ADC should 
never be shared with any digital circuitry.  Also, In- for this part 
isn't really a differential input, but operates as an "input ground". 
You can actually use that to decouple the input from both analog and 
digital ground.  Keep the input circuitry identical to the datasheet, an 
SAR ADC presents a time-varying capacitive load to the buffer amps and 
not all of them like that.

> I measured in+, in- (tied to GND), +3.3V and REF (with my Extech 82CM
> which i'm told is very accurate) and can't see any fluctuations
> beyond +-0.1mV at worst...

That doesn't tell you anything, the DVM will most certainly use an 
integrating ADC and never show anything above a few Hz.  An oscilloscope 
might do that, but it needs an active probe - passive 1:1 is loading the 
reference too much and 10:1 might be OK, but the resolution just isn't 
there.

> An interesting thing is that probing the
> circuit doesn't actually make the A/D jump, just a tiny bit when
> probing the +in - but no change in stability. Am i not to rely on
> these measurements? The only thing i can think of right now would be
> to ditch what my meter says and go ahead and experiment with adding
> tiny capacitors around the circuit... ?

Once you've assured stable inputs, the problem most likely is in the 
reference or the supply.  Since you get the correct result "most of the 
time", the noise seems to be impulsive.

The other possibility is the ADC interface itself: if it is running at 
more than about 2MHz you will likely need to add some termination.  Also 
check that you are sampling at the correct (positive) clock edge, while 
/CS should be (de-)asserted on the negative clock edge.  To that end it 
might be instructive to keep /CS asserted and check that the extra bits 
(LSB first) match up with the ones received earlier (MSB first).  If 
there is a difference, then the problem is very likely in interfacing to 
the ADC.

-- 
Achim.

(on the road :-)