[sdiy] A/D weirdness

[Magnus Danielson]

On 12/22/2011 09:40 PM, Karl Ekdahl wrote:
> I figured adding smaller bypass to the supply was a next logical step, tried a bunch but no difference :( I also added small bypasses on the REF and +IN but to no avail, the +IN even messed up the sampled values so i had to remove it.
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> I did however notice something very interesting; my assumption that some erratic behavior came from over-clocking the A/D seems to be false. I just measured the number of cycles if bypassing the delays in my routine and i got 8 cycles per period which should mean i'm way good as my processor is running 16MHz (8 cycles at 4 clocks per cycle for a PIC would mean 16 / (4 * 8) = 0.5MHz right?) so that can't be it.
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> After removing this delay and making a "history" of converted values i've noticed a pattern: out of 10 stored values (sampled at the same voltage), about 4-8 of them will be the same, some will be +/- 200 bytes, and one might be really off. Also, as im testing this by sampling the voltage from a CV keyboard and i've noticed that some keys (voltages) will almost always sample perfectly while others might have a more erratic sample history - it's repeatable so there's another pattern, i have no idea what it means tho...
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> Granted with this information i could just sample 10 times and take the value that occurs most often, but that seems like cheating - i'd rather fix whatever is being broken.

Do you sample your bits a little on the edge of things?
Could you have something else interupting your data-reading process 
somehow, so you miss timing.

Cheers,
Magnus