[sdiy] Current sink schematic/calculations help.

[ASSI]

Am Freitag, 16. Dezember 2011, 17:35:15 schrieb Justin Owen:
> I set up this schematic: http://www.sdiy.org/juz/current_sink.pdf based on

You haven't set up for biasing Q1 correctly in that schematic, which 
certainly explains some of the wierdness you see.  Also, your op-amps all 
need to be unity-gain stable with good phase margin.  The emitter of Q1 in 
your circuit will be exactly at the CV input (0..5V), but you'll want it to 
sit at some negative potential if you want to produce the Iabc for a diff 
pair.

You might try an active V-I with current mirror along the following sketch:

 buffered CV o--------+                 +--------o Iabc
                      |                 |
                    +-+-+               |
                    |   |               |
                    |   | R1            |
                    |   |               |
                    |   |               |
                    +-+-+               |
                      |    \            |
                      |    |\           |
                      |    | \          |
                      o----|+ \         |
                      |    |   >--+     |
              +-------|----|- /   |     |
              |       |    | /    |     |
              |       |    |/     |     |
              |       |    /      |     |
             ___    +-+-+         |     |
                     \|/   D1     |     |
                    __V__         |     |
                      |           |     |
                      |           |     |
                      \ |         |   | /
                       \|         |   |/
                        +---------o---+
                       /|             |\
                      v |             | v
                      |                 |
                      |                 |
                      +-----------+-----+
                                  |
                                  |
                                  o -V

D1 shifts the collector potential, a single diode assumes that the 
differential pair will be biased at 0V and hence the emitter node will be a 
diode drop below 0V (e.g. Iabc must be pulled from a source that is at 
-0.7V).  If you leave D1 out, the precision of the current mirror degrades, 
but it will still work.  The opamp keeps the voltage drop over R1 identical 
to the CV (by keeping the "foot" at 0V), so that I = V/R = Iabc.


Regards,
Achim.
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