[sdiy] FPGAs, VHDL or Verilog and why?

[James Patchell]

     Well, I use both.  Both will generate the same logic.  Generally, 
when I do a new design, I use verilog just because it is less verbose.  
Verilog will also let you hang yourself by giving you plenty of rope.  
It is a lot more difficult to do that in VHDL.

-Jim

On 12/5/2011 12:00 PM, Paul Maddox wrote:
> As the subject says,
> Which do you use and why?
>
> I've played with VHDL in the past, but a lot of people seem to think Verilog is better, so I'd like to understand which you guys use, and why, before I jump.
>
> Paul
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