[sdiy] FPGAs, VHDL or Verilog and why?

[Magnus Danielson]

On 12/06/2011 04:59 PM, Eric Brombaugh wrote:
> On 12/05/2011 04:00 PM, Magnus Danielson wrote:
>> On 12/05/2011 11:37 PM, Eric Brombaugh wrote:
>>> I use both VHDL and Verilog professionally. Given a choice I go with
>>> Verilog without hesitation. Much more concise and "C-like". Never much
>>> cared for the strong typing and verbosity of VHDL. If you like Pascal,
>>> ADA, etc. then you might like VHDL though. If you like typing large
>>> source files you also might like VHDL better than Verilog. :P
>>
>> I've never found that argument very meaningful, sure VHDL will imply
>> both pressing the keyboard a little more and it has strong typing, but
>> it has never been a real issue for me to prohibit me from doing good
>> work with VHDL, but it has saved my sorry ass several times.
>
> I know - I was mainly being snarky. Actually, while I do find that VHDL
> source files end up being longer than equivalent Verilog, most of it is
> boilerplate that only needs to be written once, then endlessly
> copy/pasted and hence has little impact on overall development time.

Well, it's a re-occuring "argument" and I think that for once could be 
replied with a more objective answer rather than the nonsense snarky reply.

I've found language misuse (in any language) is in fact a much worse 
aspect than the language itself. I've seen people attempting to be "more 
generic" loose themselves and creating problems where even the simulator 
and synthesis came up with two incompatible solutions. That didn't help 
the confusion when loosing one bit compared to what the original 
standard logic vector solution would have achieved... ah well.

So, regardless which language you also have to learn something more 
elusive, the good language usage. Part of it can be found in books, part 
of it comes with experience.

>> In the end of the day, whatever differences you can find between the
>> languages, it comes down to personal preferences and practical aspects.
>
> No doubt. It boils down to which paths in your brain are faster/wider.
> My Verilog skills are more well-worn, so that's where my comfort zone
> is. Your mileage _will_ vary in this case.

Still, many of the design aspects remains the same for both languages, 
you still want to avoid latches, think about DFF setup times, delays 
etc. etc. How you encode your design might differ a little but in the 
end it's about the same design problems you address. It's modern 
synchronous digital design regardless.

Cheers,
Magnus