[sdiy] FPGAs, VHDL or Verilog and why?

[KD KD]

2011/12/6, Magnus Danielson <magnus at rubidium.dyndns.org>:

> I've never found that argument very meaningful, sure VHDL will imply
> both pressing the keyboard a little more and it has strong typing, but
> it has never been a real issue for me to prohibit me from doing good
> work with VHDL, but it has saved my sorry ass several times.

Indeed!
The parameter of saving "sorry asses" is never to be underestimated
in an engineering situation. Tool's can make or brake projects even
if the tool itself are of sorry ass quality. It's really a two way thing.

I have seen many tools that was highly questionable but in the end
of the day saved the company's sorry ass even then choosing it in
the first place. The hill was mighty high but we made it!

Yes, later replaced that miserably piece of software to something
less sisyfosic shaped!

The older part of us that had to wander trough all the old tools now
long forgotten and put upon the big digital graveyard the younger
newer know, as they see only the tools of today and the latest upgrade!

Why are a particular set of 1 and 0 obsolete? why not self organizing
software, instant evolutionary adaptable to new external circumstances?

> In the end of the day, whatever differences you can find between the
> languages, it comes down to personal preferences and practical aspects.

Indeed.

> I keep doing my stuff in VHDL and Eric will keep doing his stuff in
> Verilog. We yet have to find out which is your preference.

Horray, for CUPL and other stone dead languages! :)

Reg
PIC24HJ