[sdiy] FPGAs, VHDL or Verilog and why?

[ASSI]

Hi Paul,

there's green grass on both side of that fence.  As long as you're doing it 
as a one-man-show, I dont think you'll find a very compelling reason to 
prefer one over the other.  Since you'll surely want to incorporate code 
written in both languages into your designs eventually, you should become 
somewhat familiar with both.  If any of your colleagues are using one or the 
other and are willing to help you learn, start with what they are familiar 
with.  Failing that, have a look at the free material available on the net.  
If you think of using those skills professionally, I'd think VHDL gets you 
further along than Verilog in Europe.

The syntactic similarity of Verilog to C (and VHDL to Ada) is really a 
"false friend" argument — you must never forget that both Verilog and VHDL 
are hardware description languages (all statements are parallel unless you 
introduce explicit ordering) and not programming languages (statements are 
sequentially ordered).  VHDL is quite a bit more verbose than Verilog, but 
with a decent editor that has templates and completion the typing is equally 
fast.  If you still can't make up your mind: "Digital Design and Computer 
Architecture" by Harris & Harris has all examples written out side-by-side 
in both languages.


HTH,
Achim.
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