[sdiy] FPGAs, VHDL or Verilog and why?

[Eric Brombaugh]

On 12/05/2011 04:00 PM, Magnus Danielson wrote:
> On 12/05/2011 11:37 PM, Eric Brombaugh wrote:
>> I use both VHDL and Verilog professionally. Given a choice I go with
>> Verilog without hesitation. Much more concise and "C-like". Never much
>> cared for the strong typing and verbosity of VHDL. If you like Pascal,
>> ADA, etc. then you might like VHDL though. If you like typing large
>> source files you also might like VHDL better than Verilog. :P
>
> I've never found that argument very meaningful, sure VHDL will imply
> both pressing the keyboard a little more and it has strong typing, but
> it has never been a real issue for me to prohibit me from doing good
> work with VHDL, but it has saved my sorry ass several times.

I know - I was mainly being snarky. Actually, while I do find that VHDL 
source files end up being longer than equivalent Verilog, most of it is 
boilerplate that only needs to be written once, then endlessly 
copy/pasted and hence has little impact on overall development time.

> In the end of the day, whatever differences you can find between the
> languages, it comes down to personal preferences and practical aspects.

No doubt. It boils down to which paths in your brain are faster/wider. 
My Verilog skills are more well-worn, so that's where my comfort zone 
is. Your mileage _will_ vary in this case.

Eric