[sdiy] FPGAs, VHDL or Verilog and why?

[Magnus Danielson]

On 12/05/2011 11:37 PM, Eric Brombaugh wrote:
> Oh - there's a "food fight" question if ever. I'll try to be diplomatic:

It sure is an issue which quickly gets dirty, but most of the fighting 
as settled by now.

> I use both VHDL and Verilog professionally. Given a choice I go with
> Verilog without hesitation. Much more concise and "C-like". Never much
> cared for the strong typing and verbosity of VHDL. If you like Pascal,
> ADA, etc. then you might like VHDL though. If you like typing large
> source files you also might like VHDL better than Verilog. :P

I've never found that argument very meaningful, sure VHDL will imply 
both pressing the keyboard a little more and it has strong typing, but 
it has never been a real issue for me to prohibit me from doing good 
work with VHDL, but it has saved my sorry ass several times.

In the end of the day, whatever differences you can find between the 
languages, it comes down to personal preferences and practical aspects.

I keep doing my stuff in VHDL and Eric will keep doing his stuff in 
Verilog. We yet have to find out which is your preference.

Cheers,
Magnus