[sdiy] FPGAs, VHDL or Verilog and why?

[Scott Gravenhorst]

Paul Maddox <yo at vacoloco.net> wrote:
>As the subject says,
>Which do you use and why?
>
>I've played with VHDL in the past, but a lot of people seem to 
>think Verilog is better, so I'd like to understand which you guys 
>use, and why, before I jump. 

I am certainly no authority, but I'll give an opinion:  When I started
with FPGA work, I looked at both.  I am a C programmer.  While neither
language is really anything at all like C, Verilog tended to _look_
like C in some ways so it seemed familiar and friendly.  VHDL looked
like some kind of alphabet soup or the output of a book pulper to me. 
I learned enough about VHDL to be able to read it.  I translated the
Xilinx Spartan-3E Starter Kit power-on design rotary encoder module
code from VHDL to Verilog just to see if I could.  I don't know about
Altera or others, but Xilinx ISE will accept modules of both languages
in the same design which relaxes the need to learn both to fluency (as
long as the modules written in the foreign language are known to work).
 As far as I know, either language can be used to build the same
design.  I think it's just a matter of what looks "right" to you. 
Verilog looks "right" to me, VHDL looks confusing to me.



-- ScottG
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