[sdiy] FPGAs, VHDL or Verilog and why?

[Magnus Danielson]

Hi Paul,

On 12/05/2011 09:00 PM, Paul Maddox wrote:
> As the subject says,
> Which do you use and why?
>
> I've played with VHDL in the past, but a lot of people seem to think Verilog is better, so I'd like to understand which you guys use, and why, before I jump.

I use VHDL. It's the only language I've learned and I can do all the 
things I really need with it. The only downside to it is that some stuff 
is done in Verilog and well, it's different.

Verilog's C-likeness doesn't get my engines going. I have both the VHDL 
and Verilog LRMs and they are quite different in weaknesses and strengths.

Here in Europe VHDL is more popular than Verilog, where as the US is the 
other way around.

I'll stick with VHDL. I work with it and made commercial designs with it 
on and off since last milenium, including an ASIC.

Cheers,
Magnus