[sdiy] A/D weirdness

ASSI Stromeko at NexGo.DE
Wed Dec 28 11:07:39 CET 2011

Am 27.12.2011 17:56, schrieb Karl Ekdahl:
> Okay so i reworked the whole thing to use the polling method where
> DOUT is tied to VCC and i check for the first '0' to come in before
> getting the data. I also get both the MSB first and the MSB last data
> and compare them afterwards - no inconsistencies so far which i
> assume means my retrieval algorithm works.

That puts the blame firmly back onto the conversion process.

> However, on that note i'm having a hard time getting my head around
> how to assure i'm polling the data on the right clock edge. I guess
> that i'd have to look real close at propagation delays etc. to figure
> this one out but i figured i'll ask anyway. Can i assume "positive
> clock edge" means "while CLK is positive"? Basically would a code
> like this work? (ugly pseudo code coming up)
> do CLK = 0;    CLK = 1; getData while

The data changes on the negative clock edge.  As long as the propagation 
delays of the clock to the ADC are the same as the ones from the DOUT 
back, the optimal sampling point then is just after the clock has gone 
high.  It sounds although as the speed of the interface is low enough 
not to cause any issues even if you'd sample later, as long as the clock 
doesn't go low again before you've finished sampling.

> Last but not least i've discovered a pattern in the inconsistent data
> that might explain what's going on here, but i'm not entirely sure
> how. Seemingly the inconsistencies i get only happen on the 8 LSBs
> and they seem to always follow a pattern of a trailing '1' or '0' -
> basically the data is never different in that a '0' or '1' happens
> alone in the middle of a data stream and always trailing - i might
> for instance get;
> 001011000
 > 001111000
 > 000011000

I suspect there is a "1" missing there, based on your explanation?

 > 001011100
 > 001001100

You seem to produce the clock by bit-banging a GPIO.  Have you checked 
that the clock is good, i.e. always has the same timing and has clean 
edges?  A too slow edge or ringing might cause the ADC to double-clock 
and it might be more susceptible to this while the SAR conversion is in 


(on the road :-)

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