[sdiy] FPGAs, VHDL or Verilog and why?
jspeth at avnera.com
Tue Dec 6 16:28:15 CET 2011
> As the subject says,
> Which do you use and why?
I was lucky enough to have to learn both at my job a couple of years ago. First VHDL for 3 months and then verilog for 7 months. My job was to come up with ways of moving some of our product code into FPGA from MCU-land. In my "free time" I designed FPGA HDL synth modules of my own designs and those found on the web. It was a lot of fun!
I personally believe that any one language will serve you equally well as the other. I think it will be a decision you'll make based on what language your closest mentor has selected or what you can find on the web (like Scott's excellent work and web site). You can learn both which is best.
I'm a C programmer too and fell for the "looks-like-C" trap in verilog coding thinking it would be easier. The syntax is familiar but the similarity ends there (abruptly). C is procedural and FPGA code is highly parallel - there's practically no common ground.
On a tangent, if you find the opportunity, try to evaluate the several C-to-H tools out there. That's quite a learning experience!
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