[sdiy] FPGAs, VHDL or Verilog and why?
ebrombaugh1 at cox.net
Mon Dec 5 23:37:04 CET 2011
Oh - there's a "food fight" question if ever. I'll try to be diplomatic:
I use both VHDL and Verilog professionally. Given a choice I go with
Verilog without hesitation. Much more concise and "C-like". Never much
cared for the strong typing and verbosity of VHDL. If you like Pascal,
ADA, etc. then you might like VHDL though. If you like typing large
source files you also might like VHDL better than Verilog. :P
On 12/05/2011 01:00 PM, Paul Maddox wrote:
> As the subject says,
> Which do you use and why?
> I've played with VHDL in the past, but a lot of people seem to think Verilog is better, so I'd like to understand which you guys use, and why, before I jump.
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