[sdiy] M110 with more outputs

[Andre Majorel]

On 2011-08-29 22:05 +0100, Neil Johnson wrote:

> The M110 takes in a 2.0024MHz clock and uses that to generate the
> four octave outputs.  The same for my M110 replacement.  To generate
> higher tones would need a higher input clock, such as 4 or 8MHz, and
> then further division to get the correct pitch.  This would be easy
> in my M110-clone as I use a 4024 divider on the compare output of
> the ATmega8's counter, and there are a further three outputs which
> could be pressed into service.  However, I don't think the counter
> would like 8MHz (the same speed as the micro - no time to
> synchronise the input).
> 
> The proper way to do it would be to do the division in an FPGA
> (e.g., Xilinx Spartan), using an on-board DLL clock multiplier to
> scale up the 2.xxMHz clock by a factor of 8, and then do the
> frequency division.

In the Mono, the clock on pin 11 comes from a VCO controlled by
the pitch bend and LFO (bottom left corner of
http://www.teaser.from/~amajorel/mono/schematics/contacts_1.png ).
Hopefully an LFO is slow enough with respect to the clock for a
PLL to work ?

> You'd also need to provide additional resistors
> to support the higher-frequency square waves, but I guess that's not
> insurmountable.

The summing is done by a 4016 (ICf7 in top left corner of
http://www.teaser.from/~amajorel/mono/schematics/main.png ). Note
the highly accurate summing network : 47 k, 100 k, 220 k, 470 k
10%. Just moving to 1% E96 values should improve things a bit.

> While I do plan on using a CPLD to implement some of the interfacing
> logic, an FPGA was not on my plans.

http://www.killgerm.com/images/product_group/534_drat_liquid_concentrate.png

Oh wait, something just occurred to me. The additional tones are
only useful in the lower end of the range. So perhaps the clock
could remain at 2 MHz and the clone produce whatever additional
tones it can for the current note.

-- 
André Majorel http://www.teaser.fr/~amajorel/