[sdiy] M110 with more outputs

[Matthew Smith]

Quoth Neil Johnson at 30/08/11 06:35...
> The proper way to do it would be to do the division in an FPGA (e.g., 
> Xilinx Spartan), using an on-board DLL clock multiplier to scale up the 
> 2.xxMHz clock by a factor of 8, and then do the frequency division. 
> You'd also need to provide additional resistors to support the 
> higher-frequency square waves, but I guess that's not insurmountable.
> 
> While I do plan on using a CPLD to implement some of the interfacing 
> logic, an FPGA was not on my plans.

I find this quite fascinating. I'd toyed with the idea of implementing a 
  TOG/divider in Verilog as it seemed a reasonably trivial exercise and 
would be good practice for me - but thought "just what do I do with a 
bunch of square waves?"  Wasn't aware of this mixed square wave technique.

Too many projects on at the moment, but certainly something to think about.

-- 
Matthew Smith

Business: http://www.smiffytech.com
Blog:     http://www.smiffysplace.com
Linkedin: http://www.linkedin.com/in/smiffy
Flickr:   http://www.flickr.com/photos/msmiffy
Twitter:  http://twitter.com/smiffy