[sdiy] 3046 vco help?

[Magnus Danielson]

On 18/08/11 23:46, Dave Kendall wrote:
> Hi all.
>
> On Aug 18, 2011, at 20:08, Magnus Danielson wrote:
>> The lower left transistor pair is the expo-pair. The collector on pin
>> 1 pulls current through from the 10 nF capacitor which is then being
>> buffered by the J112 FET which essentially acts like a emitter follower.
>> The output of that is being tossed into the upper pair which acts like
>> a comparator which with the 2N3906 acts like a reset of the
>> sawtooth.Finally, the 2N3904 is the output comparator for the square
>> signal.
>>
>> There it is. Not too odd setup. The "benefit" of this is the lack of
>> high gain in the feedback path, which can make it warmer due to the
>> inherent trigger jitter, but explaining that can be a bit tricky, but
>> I could go into that if you need me to. Fun thing. Does it sound good?
>>
>> Cheers,
>> Magnus
>
> Hi Magnus - going into the detail would be great - thanks - but like Dan
> I'm really interested - it seems like such a simple low-parts count dual
> OSC - 3046's are still available in SOIC last time I looked, and you can
> still get NOS ones if you look around..

There is nothing wrong with playing with things like this, rather the 
opposite. We can go into perfection, but loose other properties.

SOIC could be put on an adapter or the board be redesigned to fit it.

The 3046/3086 array is nice in that it becomes fairly good matching 
between the transistors in part due to the physical closeness such that 
temperature gradients has less leverage on the transistor biases. The 
uA726 with its oven and the MAT02 with its gradient-canceling layout and 
low r_BE outshines it, but r_BE may be fairly easy to compensate (see 
Buchla 258 for example).

Cheers,
Magnus