[sdiy] CMI III oscillator.

[karl dalen]

CMI Series III:

Overview: 
 Sound data is stored as 16-Bit linearly encoded sample words in a shared waveform RAM (WFM). The CMI Series III supports 16 channels of sample-playback, employing the variable-sample-rate concept for pitch variation. The CMI-35 digital cage backplane has an 8/16-Bit data/address bus (2MHz 2-slot synchronous) for the QASAR dual-6809 computer subsystem (Qxxx) and an additional 16/24-Bit data/address "WFM" bus (3.33MHz 8-slot synchronous) for the CMI waveform subsystem (CMI-xx). The 24-Bit WFM address refers to a full 16-Bit data word (with upper/lower Byte select lines), hence 16M 16-Bit words, i.e. max. 32MByte waveform RAM (older revisions used only 23 Bits, see "8-Bit mode" below; newer revisions use 25 Bits, providing 64MB address space, see MFX2 below). The 16-Bit waveform data bus is also present in a symmetrical form on the CMI-335 analog cage backplane (driven by the channel support card CMI-32) to transfer waveform data to the channel output
 modules (CMI-331, which contains the main DACs). Each channel card (CMI-31, one for two channels, each with an own control CPU) in the digital cage has a private connection to a corresponding channel output card (CMI-331, also one for two channels) in the analog cage. The sample input module (CMI-337 or CMI-346+347 or ESP-348+349, 2 channels) in the analog cage has a private connection to the waveform processor (CMI-33) or waveform supervisor (CMI-41) in the digital cage, which are responsible for waveform manipulation/loading/saving and sampling. The general interface processor (CMI-28) controls real-time events for the CMI-31s.
 The CMI Series III channel cards were developed by Adrian S. Bruce.

Sample output principle:
 Variable sample output rate for pitch variation (for each channel).
 Each CMI-31 contains 24-Bit address generators and sample rate generators for its two channels, whereas the CMI-32 provides the 16-Bit data from the waveform RAM to the output CMI-331s and the master clocks. An 8-phase "round robin" scheme (clocked by the channel support card CMI-32) for the 8 CMI-31 cards is employed for deterministic access to the shared waveform RAM at fixed timeslots (at a rate higher than the highest desired sample output rate). Each CMI-31 toggles the channel for waveform RAM access from cycle to cycle (so the total number of channels available by this method is 16). The next waveform data word (16-Bit) is loaded into a first register stage on the CMI-331s by this round robin scheme: A sample rate generator pulse (asynchronous with respect to the round robin scheme) triggers the address generator logic to load the first register (within its next following timeslot) and to compute the next address within the following round robin
 cycle for the channel. Furthermore, this pulse loads its corresponding DAC register from the first register (which at this point of time contains the previous sample value loaded by the address generator due to the previous pulse). Since the fixed round robin rate (with channel repetition rate of 208kHz, see below) is higher than the max. sample output rate, the new waveform data in the first register stage is guaranteed to be already loaded before the next sample clock pulse arrives to load the DAC register from the first register. Note that one sample clock pulse consumes only one round robin timeslot on the bus (i.e. the bus is busier with higher pitch). Each time-slot used by a CMI-31 is signalled via a common WFM-bus strobe line ("time slot taken").
 Unused time-slots are employed by the waveform processor/waveform supervisor (CMI-33/CMI-41) for WRAM refresh and waveform data read/write access.
 Compared with a theoretical, perfect sample clock rate, data from the waveform RAM arrives in the first register stage with a jitter/resolution of 4.8microsec (208kHz see below). The following second register (DAC output) with a jitter/resolution of 58 nsec (17.15MHz see below) can be considered as a jitter filter.
 The two-channel digital audio output function of the ESP-348 is realized by a serial connection to the CMI-41. Here, the CMI-41 reads the audio data directly from the waveform RAM at a fixed rate (at unsed time-slots, acting as an additional "channel card" without waveform post-processing).

 Sample input principle:
The 2-channel sample input module (CMI-337 or CMI-346+347 or ESP-348+349) provides serial audio data (via current loops with optocouplers) directly to the waveform processor (CMI-33) or waveform supervisor (CMI-41), which in turn writes the 16-Bit words into the waveform RAM (at unsed time-slots). The CMI-41 employs its on-board 68450 DMA controller for the data transfer, whereas with the CMI-33 its 68000 is directly involved. (The CMI-41 on-board SCSI controller (NCR5380) also makes use of the CMI-41 DMA controller.)

 Sample address generator principle:
 The address generators with loop capabilities for both channels are realized by a proprietary TTL state-machine with a 10MHz 24-phase micro-cycle clock (master oscillator of f_g=10MHz located on CMI-32) with various pulse-sequencer PROMs ("CLKG1", "CLKG2", "ADDGEN"). The round robin card switch rate is given by f_g/6 (approx. 3.33MHz, provided by CMI-32) which yields a card-repitition rate of f_g/(8*6) (approx. 416kHz, which also gives the 24 micro-cycles) and a channel repitition rate of f_g/(2*8*6) (approx. 208kHz). Note that the 24-Bit address remains constant until the next (asynchronous) sample rate generator pulse arrives which triggers the address generator. The waveform address incrementer kernel is implemented by an 8-Bit counter (Rev1: 2x74LS161, Rev2A: 2x74LS169) and an 8-Bit SRAM (2x2148HN-3) with various latches, registers, and glue logic. (Note: Micro-cycles have a fixed sequence with periodic pulses given by the PROMs. State-transistions
 of the glue-logic are hardwired. Hence, the design is not micro-coded, but should be considered as random-logic.) Each channel has two 24-Bit counters: one for the sample address, one for the loop end length detection. (Actually, each channel provides 2 independent loops with separate start address and length registers. At the end of the current loop, the new start address and length are read into the counter registers, with loop1/2 determined by the value of a selection Bit at that time. The end of a loop also generates an interrupt signal for the CMI-31's 68B09CPU. With Rev1, the address generator always starts with loading loop1 values. Start address, length and selection Bit values can be safely changed e.g. directly after entering the corresponding loop. With the CMI software, loop2 is employed as the "real loop". Loop1 is nothing but the region between the sample start and the "real loop"-end, and afterwards set to the block between the "real
 loop"-end and the sample-end.) Starting with CMI-31 Rev2A (May 1987), alternating looping (additional to the old forward looping) was possible. Micro-cycle PROM sequences were improved with PROM Rev2 (R2 for CMI-31 Rev1, R2A for CMI-31 Rev2A). Later revisions also provided a sample-coherent playback of the two CMI-31 channels (via shared sample clock, for use in Stereo mode, esp. MDR).

 Sample rate generator principle:
 Each channel has its own frequency divider/multiplier, consisting of a 12-Bit BRM (bit-rate-multiplier, 2x7497, basically a binary counter with Bit-selection masks) followed by a variable "octave" divider by 2^N (1.5x74LS393). It triggers the DAC registers and the address generators. The master clock for all the BRMs is located on the CMI-32 and has a frequency of f_master=34.291712MHz/2. The BRMs provide a signal consisting of not evenly distributed pulses, but the following division stages act as "jitter filters" and produce an output signal that has only "small" phase fluctuations (i.e., a jitter of 1/f_master=58nsec) left. The output rate finally reads:
 f_out=f_master*(M/4096)/(2^N) with M=1,...,4095 and N=5,...,12.
 Default tuning/no modulation sample output rate:
 C5 = 33488Hz (34.291712MHz/1024) (44.1kHz then corresponds to a shift of 4+196/256 semitones)
 Pitch resolution:
 worst case 1+1/2048 = 1/118 semitone (the CMI counts in pitch units (PU) of 1/256 semitones)
 Sample output rate range (0PU corresponds to C5):
 33Hz(-30720PU) ... 133kHz(+6143PU) (for Rev9.34, depending on rev.; note that the pitch resolution at sample output rates below 2093Hz(-12288PU) becomes worse than 1/118 semitones.)
 The CMI-31 program ("ccprog") contains a pitch-table for a full octave, translating the pitch information (in pitch units) into a BRM factor (256*12=$C00 entries).
 For analog sample input operation, the CMI-31 for CH1 is employed as the sample rate generator and CH1+2 as monitoring outputs (older revisions use CH3+4 for monitoring). In this case, the sample rate is limited to 5kHz-100kHz or 25kHz-50kHz, depending on the sample module and software.
 During MDR operation, the variable sample-rate together with the loop-end interrupt capabilities can be employed to realize a sample playback rate which is synchronized to the master-SMPTE clock. (Compare ESP-348 digital audio output: fixed playback rate given by non-synchronized ESP-348 XTAL.)