[sdiy] FracRak digital module?

[ASSI]

On Friday 22 April 2011, Barry Klein wrote:
> Why aren't there fpga's with a small pin count?

On a very fundamental level, Rent's Rule[1] and it's variations indictate 
that there should be even more pins on a typical FPGA than are possible with 
todays packaging technology - which explains the current push to 3D 
integration schemes like chip stacking etc.  Applications that use lots of 
logic, but very few I/O pins are just as rare as applications having lots of 
inherent parallelism and no communication (likely for the same reason).

On an implementation level, FPGA die size is likely determined by a yield 
vs. size tradeoff and once the die size is (at least roughly) fixed, that 
rules out certain types of packages.  Last but not least it is very common 
(and required by customers) that a single FPGA size is available in a range 
of packages and several sizes of FPGA in a single package type, limiting 
package choices even further.

But for those applications that don't need all pins and don't want to deal 
with the CSP/BGA packages, the multiple power supplies and the resulting 
requirements on PCB technology, there's a solution: just get an FPGA module 
with your choice of connector.  They typically start at DIP-40, so there's 
something for everyone.


[1] http://en.wikipedia.org/wiki/Rent%27s_rule


Achim.
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