[sdiy] FracRak digital module?

[Veronica Merryfield]

In my day job, we hit the converse - ideally we needed more pins. We had to split the design across 3 devices rather than 2 in the end - each FPGA has to have the same set of pin functions plus pins to connect to each other.

On 2011-04-22, at 10:08 AM, Scott Gravenhorst wrote:

> "Barry Klein" <Barry.L.Klein at wdc.com> wrote:
>> Dave Jones on the AmpHour podcast brought up a very good point:
>> Why aren't there fpga's with a small pin count?
> 
> I'm going to make a wild guess since I'm not a market analyst...  
> 
> Perhaps because of the amount of logic inside, it may have seemed likely that the FPGA
> would often be a do-it-all device, so many applications might need lots of I/O to
> connect to it's peripherals.  This differs from a CPU based application that is forced
> to share data busses among several peripherals which can limit the total bandwidth that
> is actually used.  With large numbers of pins, less buss sharing is required and buss
> protocols don't all have to adhere to the same rules which eases design constraints.  I
> would think that the FPGA mfrs have researched this issue and came up with the many pins
> approach out of a desire to sell as many as possible.
> 
> Outside of peripherals like ADC, DAC, etc. computational logic for applications like
> MIDI synths can be implemented entirely within an FPGA.  But this is perhaps not the
> typical application and from the FPGA mfr's standpoint, you don't have to use all the pins.
> 
> It would be interesting to know what the pin usage is for commercially made FPGA
> applications, i.e., what the consumer need has been historically.
> 
> As I said, it's a wild guess, and it is a good question indeed.
> 
> -- ScottG
> ________________________________________________________________________
> -- Scott Gravenhorst
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