[sdiy] FracRak digital module?

Neil Johnson neil.johnson97 at ntlworld.com
Fri Apr 22 22:23:25 CEST 2011


Hi,

On 22/04/2011 18:22, Eric Brombaugh wrote:
> I think Scott has the answer - market analysis shows that most 'sockets'
> for FPGAs are in designs which need a lot of I/O.
>
> Another consideration - I've made some DIY boards using FPGAs with the
> minimum pincount package which is a 100pin VQFP in Xilinx. The actual
> I/O pins on this are actually limited to around 60% of the total pins
> due to the overhead/support required: multiple power supplies for I/O,
> core & auxiliary, lots of ground pins to improve signal integrity,
> configuration and debug pins. Given the number of support pins needed
> for even a small FPGA, if you tried to squeeze it down to a 28-pin
> package you'd be left with only a dozen or so pins available for general
> I/O.

I think there's yet another factor as well.  For a given size (gate 
count, CLB count, whatever metric you choose) there will be a required 
amount of silicon.  Ideally the chip is square, and as already mentioned 
market analysis will indicate where the feature sweet spots are.  So you 
end up with a piece of silicon a certain size.  Then add in all the IOs 
that you can to give the market boys a bigger number than the competition.

But, this then means that you have a slab of silicon than won't fit into 
your ordinary DIP package once you add in the pin frame, bonding, 
packaging, etc.  So in simple terms it just doesn't fit.  Unless you 
fancy handling a 64-pin DIP?  Eeeshhh....

Why not do smaller FPGAs that will fit into a DIP?  They already exist: 
PLDs.  Fond memories of the 22V10 :)

Cheers
Neil
-- 
Synth DIY 2011 -- www.diy.synth.net/uk
Homepage -- www.njohnson.co.uk


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