[sdiy] semitones from dividers...Electronotes idea

[Dave Manley]

  On 9/19/2010 8:13 AM, dan snazelle wrote:
> There is a tiny digram which follows this information which simply shows a "divide by 196" box, which is connected to a bunch of lines and another box which is
>   labelled "decoder for 11 of 196 states".  this connects to an inverter, which then connects to one side of an AND gate, the other side of which is connected to the same signal which drives the CLOCK IN of the counter.
>
> I like the idea of being able to generate semitones from LOGIC but there is very little explanation of how to setup the decoding.

The divide by 196 counter requries 8 bits.

Simply implemented the decoder box requires 8 inverters, 11 8-bit wide AND gates, and an 11 input OR gate.

The counter has 196 states, whose binary values are:

8'b0000_0000 == 0
8'b0000_0001 == 1
8'b0000_0010 == 2
...etc
8'b1100_0011 == 195

Label these Q7, Q6....down to Q0

Invert each of these outputs to create Q7*, Q6*  down to Q0*

Pick 11 different states where you want to drop a clock pulse from the output.  An obvious choice might be 196/11 = 17.  So you will drop every 17 clock pulse.  Your decode values would be 0, 17, 34, 
...187.  For each bit in the binary representation of the state value, if the bit is a 0 use the Qn* bit, else use the Qn bit.

For example state 17 = 8'b0001_0001.  The decode for that state is then:

Q7* & Q6* & Q5* & Q4 & Q3* & Q2* & Q1* & Q0.

Wire up the 11 decodes, OR them together and you have the enable for the final clock AND gate.

You'll soon find this will require a lot of IC's, and in the old days might have instead been done in a small ROM, with the counter state used as the address, and the data at each address programmed 
with either a 1 or 0 to be used as the clock gating signal  Programmable logic was invented for this sort of thing - PALs, PLDs, (16R8, 22V10, etc). leading eventually to FPGAs.

If you try to do this be very careful with the way you gate the clock - do it wrong and you will get very small glitches on the output.

-Dave