[sdiy] Frequency follower idea. Question about FM.

[cheater cheater]

On Wed, Sep 15, 2010 at 20:48, Magnus Danielson
<magnus at rubidium.dyndns.org> wrote:
> On 09/13/2010 02:54 PM, Tom Wiltshire wrote:
>>
>> The pseudocode part of that article makes it very clear how you'd actually
>> go about implementing it:
>>
>> http://en.wikipedia.org/wiki/PID_controller#Pseudocode
>>
>> A quick look through that code makes me think that there's gains to be had
>> by making sure dt=1.
>> That simplifies it to:
>>
>> previous_error = 0
>> integral = 0
>> start:
>>   error = setpoint - actual_position
>>   integral += error
>>   derivative = (error - previous_error)
>>   output = (Kp*error) + (Ki*integral) + (Kd*derivative)
>>   previous_error = error
>>   wait(dt)
>>   goto start
>>
>> ..which is a pretty straightforward algorithm and calculation.
>>
>> I've messed around with various algorithms for LFO sync, but I've been
>> looking for ways of improving it. Simply timing the period of the sync
>> signal and setting the LFO frequency based on that works, but you either
>> have to ignore phase, or reset the phase. Resetting makes a glitch in some
>> waveforms, which generally isn't the idea. However, something that spends
>> many cycles "zooming in" on the right frequency and phase smoothly might
>> actually be worse than something that just snaps directly to the correct
>> frequency and phase once it's got it, given that LFO cycles can be quite
>> long - you probably want this thing synced this side of two minutes later!
>> Still, I'd have to hear it and play with it to be sure.
>
> LFO is certainly within the range where you run into problems with
> integrator time constants, so this is certainly best handled in digital.
> Being able to measure phase-difference with sufficient speed and precision
> is important.

I think in my idea (#2) the phase difference doesn't need to be
absolutely correct all the time. Around halfway of the phase it barely
needs to be correct (but it's best if it is repeatable at least), it's
most needed around the end of the cycle. The lack of correctness will
not change the pitch, it will only change the waveform in a nonlinear
(C^inf) way. The reset voltage of the comparator needs to be exactly
the same, or alternatively, there needs to be a proportional output of
capacitor_voltage / reset_voltage from both oscillator cores. I am not
100% sure how the system will behave if the slave oscillator has a
higher or a lower reset point than the master oscillator. I believe
that it will have a nonlinearity at the end of the cycle if its reset
point is higher (through speeding up), or a nonlinearity at the
beginning of the cycle of its reset point is lower (through slowing
down).

> The relationship between I and P for instance will control the damping
> factor/Q-value of the loop while the I parameter will control the loop
> bandwidth of the PLL. The D term will provide for quicker pull-in time as it
> differentiates the phase error such that frequency errors is better tracked
> than the weak gain for large frequency errors. Some detectors has
> phase-frequency properties, so that can be a possibility for an analogue
> implementation.
>
> A classic PLL chip is the 4046 PLL chip. It's versatile little thingie. It
> is well documented if you look around, but it is also plagued by numerous
> issues. It can be a good chip to do play with to get experience.
>
> Anyway, the field is very extensively researched, but it can be a bit hard
> to navigate it all. The BEST book
>
> http://www.amazon.ca/Phase-Locked-Loops-Roland-E-Best/dp/0071412018
>
> is a classic introductional book. Wolaver and Garner should be good
> complementary books on top of that. Then there is more specific books and
> articles for many specializations.

Thanks a lot for the tips. Will have a closer look at the chip and at
the book soon. Highly appreciated.

D.

> Cheers,
> Magnus
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