[sdiy] Typical ESR of different capacitors

[Antti Huovilainen]

On Thu, 2 Sep 2010, Tim Stinchcombe wrote:

> The problem I found with some of the app notes was that they took way 
> too simplistic an approach. You only need to add in another big cap or 
> two on the output, and you get poles and zeroes everywhere, as the ESR 
> of one cap interacts with the capacitance of another, and the regulator 
> o/p impedance forms poles with the caps and so on and so forth - the

Am I correct if I claim that the real part of the impedance the 
regulator sees is what's important?

If so, the simulation is simplified as you only need to simulate the total 
load impedance (output cap + bypass caps + possible series resistors / 
ferrites) and check that the real part is within the safe ESR area.

Quick spice simulation suggests that adding a ferrite bead and a 1-2 ohm 
ESR electrolytic cap between the regulator output cap and load should 
protect from ceramic bypass caps up to 1-2 uF in total.

Antti

"No boom today. Boom tomorrow. There's always a boom tomorrow"
   -- Lt. Cmdr. Ivanova