[sdiy] Typical ESR of different capacitors

[Tim Stinchcombe]

Hi Antti,

> I'm doing a small digital board that uses an LDO for the +5V 
> supply. This 
> requires a capacitor with relatively low ESR

Aaaarrggh!! Run for the hills! We had sooooo much trouble with something
similar at work a few years ago - all the regulator datasheets tell you how
important this is, and then don't give anywhere near enough information on
how you are supposed to use it, even if you *do* know the ESR of your
'specially-selected' low ESR cap (things like the dominant pole and gain of
the amp in the regulator are rarely given, as then at least one could model
it in SPICE). And in fact I was pretty certain that our problem was caused
by the ESR being _too low_! In the end we didn't really 'solve it' (it was
oscillating around 350kHz, from memory), we used a brute force approach with
another whopping big cap in the reg feedback loop, and really put the zap on
its gain.

Sorry, can't be much more help with the typical figures - keep looking at
manufacturers datasheets to get a feel. Kemet's SPICE program is at least
quite good in giving some idea of how ESR is affected by frequency. I
probably still have a list of refs (app notes etc.) on regulator stability,
but they're at work, so it will have to wait until tomorrow if you are
interested...?

Tim
__________________________________________________________
Tim Stinchcombe 

Cheltenham, Glos, UK
email: tim102 at tstinchcombe.freeserve.co.uk
www.timstinchcombe.co.uk