[sdiy] Guard Rings

[Dave Manley]

On 11/4/2010 9:24 PM, Oren Leavitt wrote:

>
> Looking at the pdf, you'll want to place the guard ring around the traces connecting (Q11-S, C5, R13) and (R13, Q7-G). That's your "island" of high impedance while in "hold" mode. The ring is
> connected the output (emitter) of the emitter-follower Q9 which will be at the same potential but buffered.
> Ditto for Q12, C14, R6, Q8.

I agree where the ring should go, and I'd be tempted to optimize the component
placement.

A couple of questions:

Is Q9 emitter really at the same potential as the voltage on the cap?

What's the point of R13?

David - the idea of the guard ring is to surround a high impedance node holding
a charge with a buffered potential of the same voltage.  This will isolate the
node from different nearby voltages so that it doesn't discharge due to leakage
currents on the board.  If the PCB is clean these leakage currents should be minimal.
Make sure the board is free of contamination on both sides.

-Dave