[sdiy] Saw core JFET mystery

[David G. Dixon]

> > 2N5485
> 
> The parasitic capacitances of this guy are about three times less than
> the transistor you use now plus you'd have to reduce the reset pulse
> swing by roughly another three times.  Hint, hint...

Interesting theory, Achim.  The only problems I have with it are: first, the
pinchoff voltage of 4391 is pretty variable, and can be as low as -10V,
according to the datasheet.  Hence, -15V shouldn't really be a problem.
Second, the input capacitance of 4391, while three times larger than 5485,
is still only 16pF.  This is too small to see what I'm seeing.  To prove the
point, I've taken a 22pF cap and stuck it between every possible pair of
points around the integrator-JFET-comparator circuit, and all it does is
change the magnitude and shape of the negative spike on the output, or add
some oscillation.  It certainly does nothing like what I'm seeing.

However, I have an idea, if not to cure the disease, then certainly to treat
the symptoms.  I provided for a 5.1 zener diode in my layout, between the
ramp output and ground, to eliminate a little spike which forms there just
prior to the reset (i.e., when the ramp is at 5V) in simulation.  I didn't
notice as much of a spike there in the real circuit, so I left the zener
off.  However, if I put a normal diode there instead, I can limit the
negative swing to about -0.6V.  That might just nip this thing in the bud,
by shunting whatever nastiness is accumulating there to ground before if has
a chance to bugger up the reset and kill the tracking.  I'll try it first
thing tonight.