Was '[sdiy] FPGA Synth Music' - Damaging FPGA by an Incorrect UCF Setting ?????

[cheater cheater]

What if you set it to 2.5 while the input is 3.3?

D.

On Tue, Mar 2, 2010 at 17:15, Eric Brombaugh <ebrombaugh1 at cox.net> wrote:
> On 03/02/2010 07:12 AM, Scott Gravenhorst wrote:
>>
>> I am hopeful that Xilinx designed their FPGAs so that a simple goofed up
>> UCF can't
>> actually blow out or physically damage the FPGA...
>>
>> Do I have reason to be concerned?
>
> OK, just to be sure this horse is _really_ dead, let's dig into this.
>
> The configuration option is:
>
> CONFIG VCCAUX="value";
> Where value is 2.5 or 3.3
> Example:
> CONFIG VCCAUX=3.3;
>
> Xilinx describes this further here:
>
> http://www.xilinx.com/support/answers/31375.htm
>
> As far as damage, they say:
>
> "If the CONFIG VCCAUX constraint is not set and a user chooses to change
> VCCAUX voltage to 3.3V instead of the default 2.5V, there could be problems
> with the threshold levels on the inputs. This should not cause any damage to
> the device, but the inputs to the device might not meet the higher threshold
> requirements, so there might be logic failures in your design."
>
> So, no, you won't hurt the device.
>
> They're a lot more careful about these things today. I can remember back on
> the '2000 and '3000 series parts in the early '90s it was possible to build
> a pathological bitstream that could cook the parts. You really have to work
> hard to do that these days.
>
> Eric
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