[sdiy] Saw core JFET mystery

[ASSI]

On Tuesday 02 March 2010, David G. Dixon wrote:
> I guess I'll suck off the JFET and try another one next.

I guess you are looking in the wrong place, but replace the JFET 
anyway to exclude it.  No fun fixing a circuit with a dodgy part only 
to find out that then it won't work with a good one.

Your experiments around the timing RC would indicate that there is 
insufficient decoupling from the comparator output to the input of the 
integrator; in other words you seem to integrate the reset pulse.  You 
can test this by not pulling the comparator output to -15V, but 
something like -10V to -7V -- then the injected charge should become 
lower, too.  With the low capacitance values elsewhere in the circuit 
it would not take much parasitic capacitance to become noticeable (you 
could include that cap explicitly into your circuit simulation and 
test that theory).  In part this would help the integrator reset to 
become faster as it drives the output of the opamp negative, so this 
might explain why you need less reset time constant than calculated 
and why it is detrimental to increase the reset time constant.


Achim.
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