[sdiy] Saw core JFET mystery

[David G. Dixon]

So I just tested the circuit a bit more, and if I put a 100pF capacitor
across the + input and output of the comparator (in parallel with the 22pF
one which is already there), the ramp integrator output actually dips all
the way down to about -7V.  Note that this is not just a negative spike; it
is a big J-shaped loop which adds significantly to the time of the ramp.
The integrator - input rides ground, except for a ragged-looking spike at
every reset which is only a fraction of a microsecond in duration.  Also,
the comparator output never gets higher than about -4V during the reset
even, and of course rides at -15V at all other times.

I'm really quite flummoxed by this whole thing.  I can't see how this is
even possible.  And I don't believe it has anything to do with the Franco
resistor.  Putting another one just like it in parallel causes an almost
imperceptible shift in the ramp waveform, nothing more.

I guess I'll suck off the JFET and try another one next.



> > I forgot to mention the major part of the mystery.  The thing which is
> > really causing me confusion is that if the reset timing resistor is too
> > large (i.e., significantly larger than 1k), the integrator output swings
> > well below 0V during reset.  Simulations suggest that it should simply
> ride
> > at 0V until the comparator switches off, but it can swing as low as -2
> or
> > -3V, and it is more severe at higher frequencies.  If anyone has an
> answer
> > to this, I'd love to hear it.  (I'm guessing it has something to do with
> the
> > Franco resistor...?)
> 
> Wild guesses might include inductances and overshoot, but its difficult
> to say.