[sdiy] Saw core JFET mystery

[David G. Dixon]

> WAG: is the FET junction getting forward biased?

The JFET gate is wired directly to the LM311 output, which has a 2.2k pullup
resistor to ground.  I don't see how the gate could be positive-biased with
this arrangement.  In my simulations, positive biasing of the gate will
indeed pull the integrator output negative, to about -1V max, but this
requires pulling the gate up towards +15V with a pullup resistor, and/or
increasing the size of the ground pullup resistor on the comparator output.
None of these things are in my circuit.  I had been doing this before, with
the 2N5485 JFET, and it worked well for that, but not with PN4391.

Perhaps I should try another PN4391 specimen from the bag, although in my
two years of playing with electronics I have never observed deviations in
any component of the sort of magnitude that would cause these deviations
from theory.