[sdiy] Saw core JFET mystery

[René Schmitz]

David G. Dixon schrieb:
>> What is your voltage discharge swing?
> 
> 5V ramp, 1nF cap, PN4391 JFET (rated at 30 ohms on-resistance).  The
> discharge time should be on the order of 150 to 200ns, if I'm not mistaken).

More interesting than the Ron is the discharge current, which in your 
case has to be 227mA, I = (dU * C)/t. Now you could check wether your 
FET has a larger Idss, by pulling it out of the circuit, and run apply 
5V between D on one side and G and S as the other. Measure the current. 
Theoretically thats the maximum current the FET can switch. (If we 
ignore  for a moment that one can steer the Gate slightly positive 
<600mV.) The datasheet specifies a max Idss of 150, and min of 50, so 
you might have an extreme outlier here, or there is some other source of 
discharge at work here....

> The reset circuit is simplicity itself: JFET gate wired directly to
> comparator output, 680-ohm Franco resistor (based on simulations, which are
> obviously crap), 1k timing resistor, 22pF timing cap, 2.2k comparator
> pullup.  That's it.

A drawing would help.

> I forgot to mention the major part of the mystery.  The thing which is
> really causing me confusion is that if the reset timing resistor is too
> large (i.e., significantly larger than 1k), the integrator output swings
> well below 0V during reset.  Simulations suggest that it should simply ride
> at 0V until the comparator switches off, but it can swing as low as -2 or
> -3V, and it is more severe at higher frequencies.  If anyone has an answer
> to this, I'd love to hear it.  (I'm guessing it has something to do with the
> Franco resistor...?)

Wild guesses might include inductances and overshoot, but its difficult 
to say.

Cheers,
   René






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